(1) Field of the Invention
The present invention relates to a logic circuit having a test data loading function, provided in a semiconductor chip and having a test data input function for testing a logic operation, and more particularly to a J-K flip-flop circuit having a data loading function for carrying out an input of test data other than data input for a usual logic operation.
(2) Description of the Related Art
J-K flip-flops are widely known in the art. These J-K flip-flops are used, for example, in a semiconductor chip of a gate array with a multi-stage connection to form a counter or a shift register. When the number of stages is large, it is not easy to test the counter or the shift register, especially, at the tail stages. For example, to test the m-bit of an n-bit binary counter, test data can reach the m-bit flip-flop only after 2.sup.m clocks are applied. When m=10, 2.sup.m =1024 and thus 1024 clocks must be applied. Therefore, to test a logic circuit having a very complex logic, the necessary number of clocks becomes too large and thus a very long time is needed for testing the logic circuit.
If the test data can be loaded at an arbitrary stage of the logic circuit, such an inconvenient long test time will be eliminated.
Therefore, to give a flip-flop a data loading function is especially important for flip-flops used in a logic circuit having a complex logic.
However, if an attempt is made simply to give the J-K flip-flop a data loading function, this will necessitate the use of a complex switching circuit, as later described in more detail.